1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a test structure for testing the accuracy at which conductive structures are formed.
2. Description of the Relevant Art
High yields are essential to the profitable manufacture of integrated circuits. Inspection technologies that detect fatal manufacturing defects immediately after critical processing is accordingly a very valuable tool in assuring that such manufacture will be economically successful.
A wafer fabrication process typically forms multiple integrated circuits upon each of several silicon wafers processed simultaneously. As the integrated circuits formed on a given silicon wafer are identical copies of a given product, the silicon wafer is sometimes referred to as a product wafer. An individual integrated circuit is also called a xe2x80x9cchipxe2x80x9d or a xe2x80x9cdiexe2x80x9d. Following wafer fabrication, the die are subjected to functional testing, then separated. Fully functional die are typically packaged and sold as individual units.
In general, the yield associated with a product wafer manufactured using a particular wafer fabrication process depends upon: 1) the number of steps in the wafer fabrication process, 2) the number of defects introduced during each processing step, and 3) the vulnerability of the features formed during a given processing step to the defects introduced during the processing step.
A defect is simply a flaw caused by an imperfect manufacturing process. Only some of the defects associated with a given step are xe2x80x9ccatastrophicxe2x80x9d defects, or defects which prevent an integrated circuit containing the defect from performing its intended function. It is well known that most defects occur during microstructure patterning steps. Photolithography is used to accomplish such patterning steps, during which light passing through a pattern on a mask transfers the pattern to a layer of a light-sensitive material deposited on the surface of a silicon wafer. The layer of the light-sensitive material is developed in a manner analogous to the developing of exposed photographic film. Exposure to light makes certain regions of the layer of light-sensitive material soluble. The developing step removes the soluble regions, forming holes in the layer of light-sensitive material. Select regions of the upper surface of an etchant or to dopant atoms through the holes during a subsequent processing step. Small particles (i.e., particulates) on the surface of the mask or on the surface of the photoresist layer, which block or diffuse light, cause imperfect pattern registrations (i.e., imperfect feature formations). Particulates may be present in the ambient air, introduced by processing personnel, suspended in liquids and gases used during processing, or generated by processing equipment. In general, the vulnerability of a particular feature to a given defect is inversely proportional to the physical dimensions of the feature. Thus the smaller the physical dimensions of a feature formed using photolithography, the greater the likelihood that a particulate of a given size will cause a catastrophic defect.
There are a variety of types of defects which may occur when conductive layers are formed on an integrated circuit topography. Extra material defects (xe2x80x9cEMDsxe2x80x9d) may occur when the conductive structures include material extending beyond the predefined boundaries. Such material may extend to another conductive structure causing a xe2x80x9cshortxe2x80x9d to be formed between the two conductive structures. Missing material defects (xe2x80x9cMMDsxe2x80x9d) may occur when a conductive structure is formed which is missing some of its conductive material. Such a defect may cause the formation of an xe2x80x9copenxe2x80x9d conductive structure in which the continuity of a conductive structure is broken. In addition, when forming multiple layers of conductive layers, stacked upon each other, other problems may arise. The multiple conductive layers are typically separated from each other by a dielectric (i.e., non-conductive) layer. A breakdown in the formation of this interlevel dielectric layer may allow a short to be formed between the staked conductive structures. Furthermore, conductive features on different conductive layers are typically interconnected by inter-level vertical contacts (i.e., vias). If these vias are misaligned during the processing of the conductive features, the vias may miss one or more of the conductive features it was intended to connect. Many of these defects may be tested using test structures. For example, EMDs and MMDs may be detected using specially designed test structures. Typically, these test structures include a number of electrically testable conductive lines. Electrical probing of these conductive lines may be used to determine the presence of shorts between two or more conductive lines or the presence of opens in a conductive line. FIG. 1A depicts a typical test structure used to test for EMDs. The test structure includes a first conductive comb 10 with a test pad 12 and a second conductive comb 20 with a test pad 22. The combs are formed in close proximity to each other. If no EMDs are present, electrical probing of pads 12 and 22 will show no electrical connection (e.g., high resistance). If, however, a conductive EMD 30 having a sufficient size to bridge at least two of the conductive lines is present, as depicted in FIG. 1B, a short may be formed between the two conductive lines, thus allowing an electrical connection to be formed. When pads 12 and 22 are simultaneously probed an electrical connection (e.g., a low resistance) may be detected.
FIG. 2A depicts a serpentine structure which may be used to test for MMDs in a conductive structure. The test structure includes a serpentine conductive line 40 with test pads 42 and 44 formed at both ends of the line. If no MMDs are present, electrical probing of pads 42 and 44 should show conductivity between the two pads. If, however, an MMD 50 is present, as depicted in FIG. 2B, sufficient material may be absent such that the connectivity of the conductive line is broken. This MMD may be detected when electrical probing of the pads reveals a decrease in conductivity between the pads.
A disadvantage of these types of test structures is that they are typically capable of testing for only one type of defect at a time. For example, the test structure of FIG. 1 may only be used to detect MMDs. If one or more types of defect monitoring are to be performed, typically a variety of test structures are formed on the integrated circuit topography. Since each of these test structures takes up a portion of the wafer, and since the amount of space which may be allotted to forming test structures on a wafer may be limited, the number of test structures which may be used for each type of test may also be limited. This strategy may only have limited success since a defect may occur on a test structure which was not designed to detect the presence of that defect. For example, an EMD formed on a test structure designed to detect MMD may not be detected. It would be desirable to develop a test structure and method which may rapidly determine the presence of a variety of defects, rather than a single type of defect. Such a structure and method would be beneficial in rapidly detecting the presence of unacceptable defects during production.
The problems outlined above are in large part solved by a test structure which includes a daisy chain conductive feature and conductive lines formed at two conductive feature layers, the conductive layers being separated by a dielectric layer. Portions of the daisy chain conductive feature are positioned on the first and second conductive feature layers. These portions of the daisy chain conductive feature are interconnected by vias formed through the dielectric layer. Each of the first and second conductive feature layers may also include at least one conductive line. The conductive lines of the first and second conductive feature layers and the daisy chain conductive feature may be electrically isolated from each other. This test structure allows a variety of defects to be detected using a single test structure.
In one embodiment, a multi-layer test structure includes at least a first conductive line formed at a first conductive feature layer, a second conductive line formed at a second conductive feature layer, and a daisy chain conductive feature. A daisy chain conductive feature is herein defined as a conductive feature which includes segments of conductive lines which are formed on two conductive feature layers, the conductive line segments being electrically isolated from each other at each of the conductive feature layers. The conductive line segments may be interconnected by a series of inter-level (vertical) contacts (i.e., vias) formed between the two conductive layers.
The widths of the conductive lines, as well as the spacing between them, are preferably selected to correspond to the linewidths and separation between conductive lines that may be formed in production regions of a wafer. As used in this application, xe2x80x9cproduction regionxe2x80x9d describes a region of a wafer that is designed to be a part of an operable integrated circuit intended to function as part of an electronic device targeted for use by a user of the die. Typically, the conductive lines have the minimum linewidth and spacing that will be used during a typical semiconductor processing step. Some of the conductive lines may also be formed having a variable width. Forming conductive lines having a variable width may more accurately approximate actual production features. The conductive lines may be formed by a deposition/etching procedure. Conductive lines formed from a deposition/etch may be formed from a conductive metal, e.g., aluminum, titanium, or silicided polysilicon. Alternatively, the conductive lines may be formed using a damascene process in which the conductive material is electrodeposited into a predefined trench. Conductive lines formed in this manner include copper, aluminum, tungsten or molybdenum.
A number of test pads may be coupled to the first, second and daisy chain conductive features. These test pads are configured to receive an electrical probe. An electrical probe may be used to apply a voltage to one or more test pads to determine the electrical connectivity of the various conductive features of the test structure. These test pads may also be used during voltage contrast inspection techniques.
The test structure may be used to test for defects which may have occurred during the formation of conductive features on an integrated circuit topography. The test structure may be formed on a test area of an integrated circuit topography using the same process steps as used on a production die area of the wafer. In this manner, process induced defects produced in the production die areas may be duplicated in the test structure area. Examples of test methods with which the above-described test structure may be used include, but are not limited to, voltage contrast inspection, optical inspection, and particle size distribution testing.
In another embodiment, a multi-layer test structure includes a first and third conductive line formed in a first conductive feature layer, a second and fourth conductive line formed in a second conductive feature layer, and a daisy chain conductive feature formed in both the first and second conductive layers. The addition of more conductive lines gives the test structure a higher density of conductive lines. High density test structures may be more sensitive to the presence of defects than lower density test structures.
In another embodiment, the test structure may be used to determine the approximate size range of a defect. The presence of an EMD may be detected during the electrical testing of the test structure. The conductive lines may be formed at a predetermined spacing from each other and have a predetermined width. After an EMD is detected, the test structure may be electrically tested to determine the possible size range of the defect. By determining which of the conductive lines are spanned by the defect, an approximate size range of the defect may be determined.
An advantage of the above described test structures is that a number of types of defects may be detected using a single test structure. In one embodiment, the test structures may be placed at predetermined locations of a production wafer, intermixed with production dies, to test for defects formed during the processing of production dies. Alternatively, an entire wafer may be dedicated to testing for defects during a manufacturing process. The wafer may include a plurality of test structures, as described above. The density and location of defects which may be formed during the manufacturing process may be detected before the production wafer is subjected to the processing conditions.